Digital data glitches are unwanted deviations in a data. A few causes of glitches are noise, crosstalk coupled from other lines, and transients caused by logic gates. Glitches on an input to an asynchronous sequential machine can be a serious problem. In the asynchronous environment, inputs are not validated by a periodic clock signal as they are in a synchronous state machine. In an asynchronous machine a glitch can cause: a false path to be taken, premature movement to the next state, or worst of all, oscillations or lock-up of the machine.
Glitches can occur in combinational logic unless special steps are taken to prevent them. Since most modem designs are synchronous, good synchronous design practices prevent these glitches from being a problem (i.e. no gated docks, path delay analysis for dock period determination, etc.).
Designers of asynchronous logic typically solve the glitch problem by constraining the number of inputs that can change simultaneously to one. Once constrained to single simultaneous bit changes, the designer must implement combinational logic that covers all prime implicants. Changing this combinational logic in this way is undesirable since it increases the size and delay of the circuit. This greatly limits the application of asynchronous sequential machines.
Alternately, if the bus which has multiple bit changes is coming from a synchronous domain, the single bit combinational result can be clocked. This eliminates the glitch but requires the asynchronous sequential machine to wait for the next clock. If the combinational logic is faster than the clock period, waiting is unnecessary.
One aspect of the present invention is to reduce the combinational logic required to interface combinational logic to asynchronous sequential machines. Another aspect of the present invention is to provide a performance enhancement for the multiple simultaneous bit changes for asynchronous sequential machines. Another aspect of the present invention is a digital circuit which can provide a glitch-free output for data going from a synchronous environment to an asynchronous environment or from an asynchronous environment to another asynchronous environment.